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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. d 04/28/08 is61lv2568l copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. april 2008 features ? high-speed access time: 8, 10 ns ? operating current: 50ma (typ.) ? standby current: 700a (typ.) ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? ttl compatible inputs and outputs ? single 3.3v power supply ? packages available: ? 36-pin 400-mil soj ? 44-pin tsop (type ii) ? lead-free available description the issi is61lv2568l is a very high-speed, low power, 262,144-word by 8-bit cmos static ram. the is61lv2568l is fabricated using issi 's high-performance cmos tech- nology. this highly reliable process coupled with innova- tive circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36mw (max.) with cmos input levels. the is61lv2568l operates from a single 3.3v power supply and all inputs are ttl-compatible. the is61lv2568l is available in 36-pin 400-mil soj and 44-pin tsop (type ii) packages. functional block diagram a0-a17 ce oe we 256k x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 256k x 8 high-speed cmos static ram
is61lv2568l 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 04/28/08 pin descriptions a0-a17 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 bidirectional ports v dd power gnd ground nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a4 a3 a2 a1 a0 ce i/o0 i/o1 v dd gnd i/o2 i/o3 we a17 a16 a15 a14 a13 nc nc nc nc nc a5 a6 a7 a8 oe i/o7 i/o6 gnd v dd i/o5 i/o4 a9 a10 a11 a12 nc nc nc nc 44 43 42 41 44-pin tsop (type ii) pin configuration 36-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a4 a3 a2 a1 a0 ce i/o0 i/o1 v dd gnd i/o2 i/o3 we a17 a16 a15 a14 a13 nc a5 a6 a7 a8 oe i/o7 i/o6 gnd v dd i/o5 i/o4 a9 a10 a11 a12 nc nc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. d 04/28/08 is61lv2568l absolute maximum ratings (1) symbol parameter value unit v dd supply voltage with respect to gnd ?0.5 to +4.0 v v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v t stg storage temperature ?65 to +150 c p d power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc read h l l d out i cc write l l x d in i cc dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage (1) 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min) = ?0.3v (dc); v il (min) = ?2.0v (pulse width - 2.0 ns). v ih (max) = v dd + 0.3v (dc); v ih (max) = v dd + 2.0v (pulse width - 2.0 ns). operating range range ambient temperature v dd (8ns) v dd (10 ns) commercial 0c to +70c 3.3v +10%,-5% 3.3v + 10% industrial ?40c to +85c 3.3v + 10%
is61lv2568l 4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 04/28/08 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. power supply characteristics (1) (over operating range) -8 ns -10 ns symbol parameter test conditions min. max. min. max. unit i cc v dd operating v dd = max., ce = v il com. ? 65 ? 60 ma supply current i out = 0 ma, f = max. ind. ? 65 typ. (2) ?50 ?50 i sb 1 ttl standby v dd = max., com. ? 30 ? 25 ma current v in = v ih or v il ind. ? 30 (ttl inputs) ce v ih , f = max i sb 2 cmos standby v dd = max., com. ? 3 ? 3 ma current ce v dd ? 0.2v, ind. ? 4 ma (cmos inputs) v in v dd ? 0.2v, or typ. (2) ? 700 ? 700 a v in 0.2v , f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd =3.3v, t a =25 0 c. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. d 04/28/08 is61lv2568l ac test loads ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing and reference levels 1.5v output load see figures 1 and 2 319 5 pf including jig and scope 353 output 3.3v figure 1 figure 2 z o = 50 1.5v 50 output 30 pf including jig and scope
is61lv2568l 6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 04/28/08 read cycle switching characteristics (1) (over operating range) - 8 ns -10 ns symbol parameter min. max min. max. unit t rc read cycle time 8 ? 10 ? ns t aa address access time ? 8 ? 10 ns t oha output hold time 2.5 ? 2.5 ? ns t ace ce access time ? 8 ? 10 ns t doe oe access time ? 3.5 ? 4 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzoe (2) oe to high-z output 0 3.5 0 4 ns t lzce (2) ce to low-z output 3.5 ? 3 ? ns t hzce (2) ce to high-z output 0 3.5 0 4 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 200 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. d 04/28/08 is61lv2568l t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) ( ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address ac waveforms
is61lv2568l 8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 04/28/08 write cycle switching characteristics (1,2) (over operating range) - 8 ns -10 ns symbol parameter min. max min. max. unit t wc write cycle time 8 ? 10 ? ns t sce ce to write end 7 ? 8 ? ns t aw address setup time to write end 7 ? 8 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe 1 we pulse width ( oe = high) 6 ? 7 ? ns t pwe 2 we pulse width ( oe = low) 6.5 ? 8 ? ns t sd data setup to write end 4 ? 5 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 3 ? 4 ns t lzwe (3) we high to low-z output 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or fallin g edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. d 04/28/08 is61lv2568l ac waveforms write cycle no. 1 (1,2) ( ce controlled, oe = high or low) note: 1. the internal write time is defined by the overlap of ce = low and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the data input setup and hold timing is referenced to the rising or falling edge of the signal that terminates the write. data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
is61lv2568l 10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 04/28/08 ac waveforms write cycle no. 2 (1) ( we controlled, oe = high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) note: 1. the internal write time is defined by the overlap of ce = low and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the data input setup and hold timing is referenced to the rising or falling edge of t he signal that terminates the write. note: 1. the internal write time is defined by the overlap of ce = low and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the data input setup and hold timing is referenced to the rising or falling edge of t he signal that terminates the write. data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. d 04/28/08 is61lv2568l ordering information commercial range: 0c to +70c speed (ns) order part no. package 8 is61lv2568l- 8k 400-mil soj is61lv2568l-8t tsop (type ii) is61lv2568l-8tl tsop (type ii), lead-free 10 is61lv2568l-10t tsop (type ii) is61lv2568l-10tl tsop (type ii), lead-free industrial range: ?40c to +85c speed (ns) order part no. package 10 is61lv2568l-10ki 400-mil soj is61lv2568l-10kli 400-mil soj, lead-free
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 10/29/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information 400-mil plastic soj package code: k notes: 1. controlling dimension: millimeters. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. reference document: jedec ms-027. seating plane 1 n e1 d e2 e b e a1 a c a2 b n/2+1 n/2 millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max no. leads (n) 28 32 36 a 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 a1 0.64 ? 0.025 ? 0.64 ? 0.025 ? 0.64 ? 0.025 ? a2 2.08 ? 0.082 ? 2.08 ? 0.082 ? 2.08 ? 0.082 ? b 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 c 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 d 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930 e 11.05 11.30 0.435 0.445 1 1.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 e1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e2 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc e 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc
copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 10/29/03 packaging information millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max no. leads (n) 40 42 44 a 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 a1 0.64 ? 0.025 ? 0.64 ? 0.025 ? 0.64 ? 0.025 ? a2 2.08 ? 0.082 ? 2.08 ? 0.082 ? 2.08 ? 0.082 ? b 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 c 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 d 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130 e 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 e1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e2 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc e 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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